module tb(); 

wire             aclk;
wire             rst_n;

reg   [15:0]    slave_data_re;
reg   [15:0]    slave_data_im;
reg             slave_tvalid;
wire            slave_tready;
wire   [15:0]   master_data_re;
wire   [15:0]   master_data_im;
wire            master_tvalid;
reg             master_tready;

/*rst_gen AUTO_TEMPLATE(
		  .rst_n		(rst_n),
      );*/

/*clk_gen  AUTO_TEMPLATE(
		  .ref_clk		(aclk),
      );*/

    fft_st u_fft_st(
           .clk_enable(1'b1),
           .ce_out(),
		    .reset		(~rst_n),
		    .clk		(aclk),
		
	    /*AUTOINST*/
		    // Outputs
		    .master_data_re	(master_data_re[15:0]),
		    .master_data_im	(master_data_im[15:0]),
		    .master_tvalid	(master_tvalid),
		    .slave_tready	(slave_tready),
		    // Inputs
		    .slave_data_re	(slave_data_re[15:0]),
		    .slave_data_im	(slave_data_im[15:0]),
		    .slave_tvalid	(slave_tvalid),
		    .master_tready	(master_tready));


rst_gen u_rst_gen(/*AUTOINST*/
		  // Outputs
		  .rst_n		(rst_n));		 // Templated
clk_gen u_clk_gen(/*AUTOINST*/
		  // Outputs
		  .ref_clk		(aclk));			 // Templated

tb_tx u_tb_tx(
		.aclk			(aclk),
	        .areset			(~rst_n),

		/*AUTOINST*/
	      // Outputs
	      .slave_data_re		(slave_data_re[15:0]),
	      .slave_data_im		(slave_data_im[15:0]),
	      .slave_tvalid		(slave_tvalid),
	      .master_tready		(master_tready),
	      // Inputs
	      .slave_tready		(slave_tready),
	      .master_data_re		(master_data_re[15:0]),
	      .master_data_im		(master_data_im[15:0]),
	      .master_tvalid		(master_tvalid));		  
		  

dump dump();

endmodule
